Multilayer PCB (4–12 Layer, FR4)

IPC-A-600 Class 2 vs. Class 3: Choosing the Right Standard

IPC-A-600 defines acceptability criteria for PCB manufacturing. Choosing the correct class has cost and lead time implications:

Class 2 (General Electronics Products). Covers most commercial, industrial, and consumer electronics. Allows for minor cosmetic imperfections (e.g., minor laminate voids, certain surface blemishes) that do not affect functionality or long-term reliability. The correct choice for most IoT, consumer electronics, and general industrial products.

Class 3 (High Performance/Harsh Environment). Required for medical, aerospace, military, and safety-critical industrial applications. Tighter tolerances on conductor width, annular ring, and surface finish integrity. Rejects boards that would pass Class 2. Expect a 15–30% price premium and longer inspection times.

If your end product does not explicitly require Class 3 (check with your end customer’s quality specification), specifying Class 2 avoids unnecessary cost. Over-specifying Class 3 for a consumer IoT device is a common mistake that adds cost without improving end-user reliability.

ENIG vs. HASL: Surface Finish Trade-offs

ENIG (Electroless Nickel Immersion Gold). Flat surface for fine-pitch components (0.5mm QFP, 0.4mm BGA). Good shelf life (≥12 months). Better for SMT assembly line coplanarity. Required for wire bonding and press-fit connector applications. 20–40% more expensive per panel than HASL.

HASL Lead-Free. Hot Air Solder Leveling with lead-free solder (SAC305 or similar). Lowest cost surface finish, robust solderability, adequate for 0.8mm pitch and coarser. Uneven surface texture makes it unsuitable for components with <0.65mm lead pitch or small BGA packages. Good choice for through-hole dominant boards or prototype runs where cost matters most.

OSP (Organic Solderability Preservative). Flat like ENIG, cheaper than ENIG, but shorter shelf life (3–6 months before solderability degrades). Suitable for high-volume boards assembled quickly after manufacture. Not recommended for staggered assembly or boards stored >6 months before use.

For mixed SMT + through-hole designs with 0.5mm QFP or BGA components, ENIG is the standard choice despite the cost premium.

Controlled Impedance Verification

High-speed PCB designs (USB 3.0, HDMI, DDR, RF traces) require controlled impedance traces. A factory claiming controlled impedance capability should provide:

1. Impedance test coupon. Each production panel should include a test coupon (typically a 150mm trace segment) used to measure actual impedance with a TDR (Time Domain Reflectometer). The coupon is part of the panel but not the functional board.

2. Test report. The factory should provide a TDR measurement report for each lot, showing measured impedance vs. target (e.g., 50Ω ± 10%, or 90Ω differential). Without this report, controlled impedance is unverified.

3. Stackup documentation. Request the exact stackup (dielectric thickness, copper weight, and dielectric constant for each material layer) used for impedance calculation. The stackup determines whether the stated impedance is achievable with the requested trace geometry.

Gerber File Checklist Before Placing an Order

Sending incorrect or incomplete Gerber files is the most common cause of prototype rework. Before submitting:

• Confirm layer stack (Gerber file names must match layer assignments)
• Check that the board outline (Edge Cuts layer) is a closed polygon — open outlines cause routing errors
• Verify drill file uses the same coordinate units as the Gerber files (metric vs. inch)
• Include an IPC-D-356 netlist for electrical testing (E-test)
• Specify surface finish, copper weight, board thickness, and IPC class in the fab notes — do not leave these fields blank

Most DFM (Design for Manufacturability) errors are caught during the factory’s CAM review, but catching them before submission saves 2–3 days of back-and-forth.