ESD Protection in Electronics: PCB Layout & Design

ESD (electrostatic discharge) damages electronics in two ways: catastrophic failure (immediate, obvious) and latent damage (weakened gate oxide or junction, reduced reliability, field failure after 6–18 months). Latent ESD damage is the dangerous one — it passes all factory tests, ships, and fails in the field. Both types are prevented by correct circuit protection design and ESD-safe handling during manufacturing.

Overview

ESD events happen when a charged object (human body, machine, component) rapidly discharges into a circuit. The discharge is characterized by peak current (tens of amperes), rise time (nanoseconds), and total energy (microjoules). Gate oxides in modern CMOS (2–5 nm thick in 28 nm process nodes) break down at voltages as low as 1–2V across the gate. ESD events typically deliver hundreds to thousands of volts to the device terminals.

There are two distinct ESD problems:

Component-level ESD (during manufacturing and handling): governed by HBM, CDM, and MM models; protected by handling procedures and EPA (ESD Protected Area) in the factory.
System-level ESD (during end-use): governed by IEC 61000-4-2; protected by TVS diodes, transient filters, and PCB layout at the design level.

Both must be addressed. Good factory handling does not compensate for missing circuit protection, and good circuit protection does not compensate for ESD damage inflicted during manufacturing.

Key Parameters

Discharge Models for Component-Level ESD:

Model	Abbreviation	Equivalent Circuit	Typical Damage
Human Body Model	HBM	100 pF + 1.5 kΩ series	Gate oxide breakdown, junction damage
Charged Device Model	CDM	Low R, capacitance = device package	Gate oxide; faster, lower energy but more damaging
Machine Model	MM	200 pF + 0 Ω	Largely deprecated; rarely tested

System-level ESD test levels per IEC 61000-4-2:

Level	Contact Discharge	Air Discharge	Typical Application
Level 1	±0.5 kV	±1 kV	—
Level 2	±1 kV	±2 kV	—
Level 3	±2 kV	±4 kV	Commercial, CE marking
Level 4	±4 kV	±8 kV	Industrial, IEC 61000-6-2
Special X	>±4 kV	>±8 kV	Specified per product standard

IEC 61000-4-2 Level 3 (±2 kV contact, ±4 kV air) is required for CE marking under EMC Directive (EN 55032 / EN 61000-6-1 for residential, EN 61000-6-2 for industrial). Level 4 is typically required for industrial equipment.

Component-level ESD ratings for ICs:

IC Class	HBM Withstand Voltage	Handling Required
Class 0	<250 V	Extreme care; rarely seen in modern design
Class 1A	250–499 V	Full ESD precautions required
Class 1B	500–999 V	Full ESD precautions required
Class 1C	1,000–1,999 V	Standard ESD precautions
Class 2	2,000–3,999 V	Standard ESD precautions
Class 3A	4,000–7,999 V	Some precaution

Most modern microcontrollers (STM32, ESP32, nRF52) have internal ESD protection at the pad level and achieve HBM Class 2 or Class 3A. RF front-end ICs, LNAs, and high-speed ADCs are often Class 1 — handle with full EPA precautions.

ESD Protection Devices

TVS Diodes (Transient Voltage Suppressor) The primary protection device for system-level ESD. Two types:

Unidirectional: protects against one polarity (positive transient). Lower clamping voltage; used for power rails where negative transients don’t occur.
Bidirectional: protects against both polarities. Used for signal lines, data buses, USB, HDMI.

Key TVS specifications:

Parameter	What It Means	Typical Values
Standoff voltage (VRWM)	Maximum continuous voltage; TVS is transparent below this	5 V, 12 V, 24 V…
Breakdown voltage (VBR)	TVS begins to conduct; 10% above VRWM typically	5.5 V, 13.3 V
Clamping voltage (VC)	Peak voltage at peak pulse current (Ipp)	1.2–1.5× VRWM
Peak pulse current (Ipp)	Maximum pulse current per JEDEC pulse standard (8/20 µs)	5 A, 10 A, 30 A
Capacitance	Parasitic capacitance that loads the signal line	0.5–100 pF typical

Capacitance matters: For USB 2.0 (480 Mbps), ESD protection capacitance must be <1 pF to avoid signal degradation. For USB 3.0 (5 Gbps), <0.3 pF. Use rail-to-rail steering diode arrays (e.g., Littelfuse PRTR5V0U2X, 0.35 pF) for high-speed interfaces. For slow signal lines (<1 MHz), 5–100 pF is acceptable.

Recommended TVS selection by interface:

Interface	Recommended Device	Vc	Cap
USB 2.0	Littelfuse PRTR5V0U2X	6 V	0.35 pF
USB 3.0/3.1	Bourns CDNBS08	6 V	0.15 pF
HDMI	ST HDMI05	8 V	0.3 pF
RS-485	Semtech SM712-02	12 V	30 pF
General I/O (5V)	Littelfuse SP0503BAHT	8 V	1 pF
Power rail (12V)	Vishay SMBJ12A	19.9 V	N/A

Multilayer Varistors (MLV) Metal oxide varistors in ceramic package. Bidirectional, large capacitance (100–1000 pF). Good for power lines, AC inputs, and lines where high capacitance is acceptable. Lower repeatability than TVS diodes; varistor response degrades after repeated strikes.

PCB Layout Rules for ESD Protection

Layout is critical — even a correctly selected TVS diode fails to protect if placed too far from the connector. Rule: ESD protection must intercept the surge path before it reaches the IC. Place TVS devices between the connector and the first IC in the signal path, with the shortest possible trace between them.

Priority layout rules:

Place TVS footprint immediately adjacent to the connector pad (0.5 mm maximum trace length from connector pin to TVS anode)
TVS cathode connects to the ground plane via a short, wide trace — not through a long loop
Ground plane under the protection zone (between connector and TVS) should be solid copper, no slots or relief (slots add inductance, inductance adds voltage spike during transient)
Protected signal trace should not run parallel to an unprotected trace near the connector area — crosstalk couples ESD to adjacent lines

Guard rings: For isolated high-impedance nodes (analog inputs, MEMS sensor connections), a guard ring around the trace connected to a stable potential prevents field induction from nearby ESD events.

ESD-Safe Manufacturing Requirements

IEC 61340-5-1 defines requirements for EPA (ESD Protected Area) in electronics manufacturing:

EPA Element	Requirement
Floor	Dissipative (resistance 1 MΩ–1 GΩ) or conductive (<1 MΩ)
Work surface	Dissipative or conductive, grounded
Wrist strap	<35 MΩ system resistance to ground; tested daily
Footwear + floor	System resistance <100 MΩ (footwear + floor in series)
Packaging	Dissipative bags or Faraday cage bags for all Class 0/1 components
Ionizer	Required at workstations where grounding is impractical (boards in fixtures)

Ask your factory:

“Do you have a documented EPA and EPA certification?” (should say yes for any ICs)
“How often do wrist straps get tested?” (answer should be: daily, with records)
“Where are your ionizers installed?” (should be at final assembly and test benches)
“How do you handle BGAs and RF modules from reel to machine?” (answer should describe ESD bags and grounded tray handling)

A factory that has SMT machines, automated test, and no documented EPA is a red flag — all those humans handling boards between process steps are potential ESD events.

What to Specify When Ordering from China

EPA requirement: state “all ESD-sensitive components (ESDS) must be handled in EPA per IEC 61340-5-1” in your quality agreement
TVS device MPN: do not specify just “ESD diode on USB lines” — specify the exact MPN (e.g., Littelfuse PRTR5V0U2X) in the BOM; generic ESD diodes vary enormously in capacitance and clamping characteristics
IEC 61000-4-2 test level: state the required ESD immunity level for the assembled product in your product specification, so the factory knows what the end requirement is (even if they don’t do the system-level test)
Moisture and ESD dual handling: ESD-sensitive BGAs are also often MSL 3 — require that components be stored in ESD bags AND sealed moisture barrier bags until reflow

Common Issues

Latent ESD damage in the field: Product passes all factory tests, ships, and fails 6–18 months into service with random, hard-to-reproduce faults. Often traces to gate oxide degradation from multiple low-level ESD events during manufacturing without EPA. Prevention: factory EPA certification + wrist strap records + audit of handling procedures.

ESD compliance is a systemic process issue, not a component one — which makes it a core topic in PCB assembly sourcing audits. Pre-shipment inspection cannot reliably catch latent ESD damage after the fact; the correct intervention is verifying EPA procedures at the factory before production begins. For consumer electronics products in particular, where warranty return rates are visible and attributable, latent ESD is consistently worth auditing even when the component datasheets look correct.

TVS diode placed on wrong side of common-mode choke: On USB and Ethernet lines, a common-mode choke (for EMI) is often in series with the data line. If the TVS is placed on the IC side of the choke, the choke inductance appears in series with the surge path, raising the clamping voltage seen by the IC. Place TVS between connector and choke, not between choke and IC.

Inadequate ground return for TVS: TVS diverts surge current to ground via its cathode. If the ground trace from TVS cathode to the nearest ground plane via has significant inductance (long trace, narrow trace, no plane below), the inductive voltage spike (V = L × dI/dt) adds to the clamping voltage seen by the IC. For a 10 A/ns rise time surge (IEC 61000-4-2 ESD waveform) into 1 nH of ground inductance, the added spike is 10 V — enough to damage a 5 V IC even with a correctly specified TVS.

SMT Assembly Process — manufacturing process where ESD damage most commonly occurs
IPC-A-610 Acceptance Criteria — workmanship standards relevant to ESD handling
DFM Guidelines — PCB design rules that support ESD protection
PCB Substrate Materials — material choice and ESD dissipative properties
Factory Audit Checklist
How to Source Electronics from China
Quality Inspection Services
PCB Manufacturing & SMT Sourcing
Consumer Electronics Sourcing